CMOS field-effect transistors exhibit the characteristics of high switching speeds and high noise immunity over a wide range of power supply voltages. As such, they are commonly used in such devices as wrist watches, hand-held calculators and in other environments where low power consumption is desirable.
In the prior art, the most typical way to introduce a well of opposite seminconductor type is to introduce the well as the first step in a CMOS fabrication process prior to constructing the balance of the circuit. This is accomplished by using a mask to selectively introduce dopants into areas where wells are desired and then driving the dopants to make a well.
Because the construction of P and N channel transistors differs in a variety of ways, multiple masks must be used which are practically identical to the well mask, to selectively introduce wells into regions of the wafer where needed.
In the prior art, high voltage CMOS devices have used field oxides and heavily doped substrates and wells to reduce leakage between neighboring active MOS areas. In particular, if a reasonably high field threshold is desired, at least one, and more often two, masks are required to accomplish this field threshold adjustment. These masks are identical to the well mask pattern, except perhaps for their size. But such devices generally exhibit unsatisfactory AC performance, as such devices exhibit high threshold voltages and high capacitance.
To reduce leakage problems without employing thick field oxides and heavily doped substrates, various full channel stops spaced apart from the active devices which they surround have been proposed. Techniques, such as ion implantation, are employed requiring rather complex processing conditions involving a number of masking steps in addition to those required in the formation of the active devices. As such, the channel stops are not self-aligning with the active elements.
U.S. Pat. No. 4,013,484 discloses and claims a method of forming channel stops while reducing the number of additional masking steps previously required. In doing so, the referenced patent teaches the creation of channel stops of opposite conductivity type in a silicon substrate between first and second spaced apart active regions. In practicing that invention, certain deficiencies persist.
For example, in providing a p-well and corresponding channel stops of sufficient width to provide the necessary isolation, the p-type material is driven deeply into the silicon substrate diminishing the utility of the invention in high density applications. As with the prior art, the process disclosed in U.S. Pat. No. 4,013,484 teaches a method for producing channel stop regions which are not self-aligned to the p-well boundary. Further, because of the depth to which the channel stops must be driven to fully isolate the active regions, reduction in source-drain junction breakdown voltage is experienced as well as a corresponding increase in source-drain side wall capacitance.
It is thus an object of the present invention to provide a method for fabricating CMOS transistors without experiencing the difficulties outlined above.
It is yet another object of the present invention to provide a method for fabricating CMOS transistors with self-aligned field regions without employing additional masking steps other than the single masking step used to define the p-well region.
It is yet another object of the present invention to provide a method of fabricating CMOS transistors allowing a minimum space to be used to separate the n-channel and p-channel transistors.